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Description: 基于XILINX公司的型号为FPGA，使用用VHDL语言编写的ADS8681驱动程序。(Based on the XILINX company's model FPGA, we use the ADS8681 driver written in VHDL language.)
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Size: 420864 |
Author: 阿斯顿爱爱时 |
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Description: In this paper, a FPGA-based step motor driver implementing adjustable subdivision and sine pulse width modulation is introduced. This driving system can solve the high subdivision problem, increase the driving torque and angle resolution, and smooth the motor angle. Employing the bottom-top design method, the circuit was described by the VHDL language, synthesized by Xilinx ISE integrated environment, and simulated by Modelsim in both behavior level and gate level through the PLI interface. According to experiment’s result, this driver has the advantages of easy debugging, high anti-interference ability, larger driving power, low volume and low cost in large scale production.
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Size: 623104 |
Author: jionad123 |
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Description: Parallel FIR filter is the prime block of many modern communication application such as MIMO, multi-point transceivers
etc. But hardware replication problem of parallel techniques make the system more bulky and costly. Fast FIR algorithm
(FFA) gives the best alternative to traditional parallel techniques. In this paper, FFA based FIR structures with different
topologies of multiplier and adder are implemented. To optimize design different multiplication technique like add and
shift method, Vedic multiplier and booth multiplier are used for computation. Various adders such as carry select adder,
carry save adder and Han-Carlson adder are analyzed for improved performance of the FFA structure. The basic objective
is to investigate the performance of these designs for the tradeoffs between area, delay and power dissipation. Comparative
study is carried out among conventional and different proposed designs. The advantage of presented work is that; based on
the constraints, one can select the suitable design for specific application. It also fulfils the literature gap of critical analysis
of FPGA implementation of FFA architecture using different multiplier and adder topologies. Xilinx Vivado HLS tool is
used to implement the proposed designs in VHDL.
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Size: 1123027 |
Author: nalevihtkas |
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